1. Field of the Invention
The present invention relates to an integrated circuit layout design supporting device, an integrated circuit layout design supporting method, a program, and a data structure thereof.
2. Description of the Related Art
For designing layout of a large-scaled integrated circuit (for example, LSI), widely used is a method which enables a designing period to be shortened by dividing a chip into pieces of a design unit called a macro (macro block) by a hierarchy layout style and performing layout processing of each macro block in parallel.
In such layout designing of an LSI that uses a plurality of macro blocks including a same function, it is considered to use a plurality of same macro layout patterns on a chip of the LSI for improving the designing efficiency. FIG. 32 and FIG. 33 illustrate such related technique. FIG. 32 is an illustration for describing an example of wiring layout processing between macro blocks performed by a layout design supporting device of the related technique. FIG. 33 is an illustration for describing a wiring layout state after completing layout of a chip.
As shown in FIG. 32, macro blocks 1001a, 1001b, 1001c, and 1001d are arranged within a top hierarchy of a chip 1000. Among those, four macro blocks 1001a are same-types of macro blocks that include a same function. In addition to those, there are a plurality of different types of macro blocks 1001b, 1001c, and 1001d illustrated in FIG. 32. For the same-types of four macro blocks 1001a, already-designed macro blocks, and the like are used. Thus, a pattern of internal functional elements (for example, logic circuit elements) and position of macro terminals 1002 are normally fixed. After arranging each of the macro blocks 1001a, 1001b, 1001c, and 1001d, wiring layout processing is performed to form a wiring 1003 between each of macro terminals 1002 in areas between each of the macro blocks 1001a, 1001b, 1001c, and 1001d. Thereafter, wiring layout processing within each macro block is performed to form layout of the chip 1000 after being wired, as shown in FIG. 33.
Further, as related techniques of an LSI layout design supporting device of this type, there are techniques depicted in Patent Document 1—Patent Document 5 shown in the followings, for example.
In Japanese Unexamined Patent Publication H3-209848 (Patent Document 1), schematic wiring processing between each of functional blocks (macro blocks) of a semiconductor integrated circuit is performed, and a wiring priority direction is determined based on a result of schematic wiring paths obtained after performing the schematic wiring processing and a coordinate positional relation between terminals and sides on the schematic wiring paths. Then, the position of the terminal whose position does not match the wiring priority direction is changed according to the wiring priority direction to re-determine the position of that terminal. As described, Patent Document 1 discloses a technique to shorten the wirings between each of the functional blocks as much as possible by changing the terminal position in each functional block (upper right part on p. 2—lower left part on p. 3).
An integrated circuit designing device disclosed in Japanese Unexamined Patent Publication H4-60873 (Patent Document 2) includes: a provisional layout device which arranges provisional macro blocks whose internal layout is not done, sets virtual external terminals, and performs layout processing of an entire chip and schematic wiring processing; an external terminal position setting device which determines positions of external terminals of each macro block based on a result of the provisional layout; a macro block layout designing device which designs layout of inside each macro block based on the determined positions of the external terminals; a wiring device for performing detailed wirings of the entire chip; and a macro block changing device which changes the determined positions of the external terminals by defining external form of the macro blocks anew (upper right part on p. 3—lower left part on p. 3). With this structure, a plurality of macro blocks are arranged on a chip, and wirings inside the macro blocks and wirings between the macro blocks are set provisionally. Then, after checking the entire layout, size of the macro blocks, layout positions of the terminals, wiring paths, and the like are changed as necessary.
Japanese Unexamined Patent Publication H11-307644 (Patent Document 3) discloses a technique which, in a hard macro designing flow, copies macro layout wiring information for the number of macros (macro blocks) loaded on a chip to chip layout wiring information, and changes the macro names within the chip layout wiring information to which the macro layout wiring information is copied so that the macro names correspond on one on one basis with the macro names of circuit connection information (logic circuits, input/output terminals, wirings, etc.) of the macros in a hierarchical structure (hierarchical illustration in FIG. 6B of Patent Document 3) (paragraph numbers 0038, 0049).
Further, Patent Document 3 discloses a technique to move (offset) the macros to desired loading positions within the chip layout wiring information based on automatic wiring library and offset information (for example, arranged coordinates of logic circuits within macros, wiring coordinates between each of the logic circuits, coordinates of the macros to be loaded on the chip) stored in a library storage part, and create the layout wiring information of the chip where the macros are offset (moved to prescribed positions) (paragraph numbers 0038, 0049). Thereafter, a chip automatic wiring tool is used to readout the circuit connection information of the chip including the macros of hierarchical structure, the automatic layout wiring library of the chip, and the layout wiring information of the chip where the macros are offset, and create layout wiring information with the macros only (paragraph numbers 0038, 0050). Furthermore, the automatic wiring tool of the chip is used to automatically arrange other logic circuits, create layout information, performs automatic wiring, create layout wiring information, checks the result of the layout wiring and the wiring length, and complete the chip designing (paragraph numbers 0030-0034).
Further, Patent Document 3 discloses a technique which inverts the macros in the X-axis direction and the Y-axis direction or rotates the entire macros when offsetting the layout positions of the macros within the layout wiring information of the chip (paragraph number 0076).
Japanese Unexamined Patent Publication 2001-319976 (Patent Document 4) discloses a structure which selects a terminal to be used from a plurality of same function terminals provided in different sides of a macro (macro block) (paragraph numbers 0026-0027). More specifically, as shown in FIG. 34, a macro block 1010 includes same function terminals (an, bn, ae, be, aw, bw, as, bs) in the fours sides of that macro block 1010. When performing wiring processing between the macro blocks, the terminals in one side (as, bs, for example) with which the wiring between the macro blocks becomes short are selected from a plurality of same function terminals (an, bn, ae, be, aw, bw, as, bs). For the macro input terminals (an, ae, aw, as), only one macro input terminal (as) is used in the wiring processing among the plurality of the terminals. Other unused macro input terminals (an, ae, aw) are subjected to clamp processing on the top layout for being fixed to having logic of 0. The clamp processing means to generate clamp cells CS to be wired to the macro input terminals (an, ae, aw).
Japanese Unexamined Patent Publication 2005-332053 (Patent Document 5) discloses a layout design supporting device which, among a plurality of units (macro blocks) obtained by dividing the top, designs layout of only a single representative unit of a plurality of same structure units except for names of signals. The layout design supporting device designs layout of the top including passing wirings on the plurality of the same units and applies all the passing wirings to the representative unit, while providing macro pins on the boundary of the passing wirings of the representative unit, and fixing the macro pins to design the layout of the representative unit.
When a plurality of same-type macro blocks are used on the chip, an optimum result cannot be achieved in some cases, because the circuit delay in a system LSI in timing designing cannot be set within a range of delay required for achieving a normal operation, due to the wiring property between the macro blocks depending on the layout regarding the same-type macro blocks and other different types of macro blocks formed in the surroundings thereof.
Specifically, the layout within the macro blocks needs to keep the uniformity, so that the positions of the macro terminals that are the external terminals of the macro blocks are all need to be identical. For trying to perform the wiring processing of the top layout by using the same-type macro blocks as described above, a part of the wiring 1003 between the macro blocks becomes detoured in the layout of the top hierarchy as a result, as shown in FIG. 32 and FIG. 33. Therefore, the wiring length is increased, which results in deteriorating the wiring property of the entire LSI and deteriorating the wiring delay time.
In Patent Document 1, the terminal positions (positions of the macro terminals) of each functional block (macro block) can only be changed gradually, and the wiring priority direction is limited to the horizontal direction or vertical direction. Thus, even if the terminal positions are changed, the wiring still needs to be detoured. Therefore, the wiring length is increased.
Further, in Patent Document 1, it is necessary to change the terminal positions, wirings, and the like again after performing the schematic wiring processing, which results in increasing the number of unnecessary processing steps.
In Patent Document 2, the terminal positions are changed by even changing the size and the shape of the macro block. Thus, when a plurality of same-type macro blocks are to be used, the uniformity of each macro block cannot be secured. Further, assuming that a plurality of the macro blocks of Patent Document 2 are used and formed on a chip 1030, a bypass wiring part 1032 is generated within a macro block area even if the terminal position of the macro block that needs to be changed to a terminal position is changed to that position as shown in FIG. 36. Therefore, the wiring length becomes increased. Furthermore, it is necessary to perform correction after provisional layout is performed once by the provisional layout device, so that the number of unnecessary processing steps is increased.
In Patent Document 3, macro blocks are copied on a chip, and the macro blocks are moved to specific positions by offset processing. Thereafter, wiring processing between the macro terminals is performed. Because of the offset processing performed to move the macro blocks from the position copied and arranged to other specific positions, etc., the number of processing steps is increased.
Further, in Patent Document 3, a plurality of macros (macro blocks) are copied and only a plurality of same-type macros are used. Thus, with the layout under a condition where the plurality of same-type macro blocks and other types of plural macro blocks that are different from each other are mixed, it is also necessary to use a bypass wiring like the case of FIG. 32, if the macro blocks of Patent Document 3 are used because the macro terminals of the macro blocks used therein are fixed. Therefore, the wiring length becomes increased.
Further, when the macro blocks of Patent Document 3 are used in the layout shown in FIG. 32, it is considered to invert the macro blocks in the X-axis direction or the Y-axis direction or to rotate the entire macro blocks by performing the offset processing for offsetting the layout positions of the macro blocks. In that case, it is necessary to perform the processing such as rotating the macro blocks for the number of macro blocks that cannot finely fit in the positional relation. This increases not only the number of processing steps but also the amount of calculation for rotating or moving the macro blocks as well as the time required for the processing. In particular, under a condition where a great number of macro blocks are used and each of those needs to be arranged in different directions, the number of processing steps is increased still more.
Further, in Patent Document 3, when moving the macros to prescribed loading positions in the layout wiring information of the chip by the offset processing performed after copying the macros, it is necessary to move each of a plurality of copied macros individually. Therefore, the names of the macros are changed for discriminating each macro before the offset processing, because the macros are not discriminated before the change in the wiring connection information of the chip generated by copying (wiring connection information of) the macros, even though each of the macro names is discriminated in the circuit connection information of the chip which shows the hierarchical structure. However, assuming that a plurality of macro blocks of Patent Document 3 are used in the case of FIG. 32, it is necessary to perform the offset processing for each of the plurality of macro blocks even if the macro names are changed. Further, since bypass wirings are formed within the macro blocks, the total wiring length of the chip as a whole can not be formed short.
Furthermore, in Patent Document 3, in a case where a desired wiring can not be achieved by automatic wiring in the wiring processing on the inside the macro or the like, the automatic wiring needs to be corrected by a manual wiring function of the automatic layout wiring tool of the chip as necessary (paragraph number 0025). Further, the automatic layout wiring tool is also utilized for the wiring processing outside the macros. In that case, it is necessary to check the wiring length within the macro blocks and between the macro blocks and to correct the wiring when it is found that the automatic wiring is not in a desirable state. Thus, there is required more time for the processing. That is, in Patent Document 3, it is necessary to correct the wiring within the macro blocks and to correct the wiring between the macro blocks in addition to performing the offset processing. Therefore, the number of processing steps is increased.
With Patent Document 4, it takes time and effort to perform clamp processing to each of the unused macro input terminals on three sides among the four sides of the macro block. For example, as shown in FIG. 34, it is necessary to perform clamp processing for each of the three input terminals aw, an, and ae except for the macro input terminal, as, to be used. At that time, clamp cells CS and wirings for connecting the clamp cells CS and the terminals (an, ae, aw) are required. If a plurality of the macro blocks 1010 in such structure are to be used, it becomes necessary to perform clamp processing on each of the unused terminals for each macro block. Thus, there is required still more time and effort.
For example, as shown in FIG. 35, in the case of a chip 1020 that uses a plurality of macro blocks 1010 of Patent Document 4, it is necessary to include the clamp cell CS and a wiring for one macro block 1010 in addition to including the clamp cell for performing the clamp processing to the above-described unused terminals and wiring between the clamp cells CS and the unused terminals for another macro block 1010. Moreover, the three sides requiring the clamp processing in each macro block are at different positions, so that the clamp processing needs to be performed in accordance with the surrounding conditions. Thus, it requires time and effort for performing the processing, and the number of processing steps is increased. Further, the clamp cells as well as the wirings for connecting the unused terminals and the clamp cells CS need to be provided outside the area of the macro block 1010, thereby increasing the number of unnecessary elements and wirings. This causes delay in the processing speed and increase in the power consumption of the entire chip.
Furthermore, with Patent Document 4, as shown in FIG. 34, in an actual functional macro area (internal core circuit) 1011 functioning actually as a macro (aggregate of logic elements) of the macro block 1010, it is necessary to provide a plurality of new logic elements called terminal selecting devices in an area (terminal selecting device area) between reference numeral 1012 and reference numeral 1013 for giving multiplicity of the use to the terminals on each side. In addition, it is necessary to secure a larger space for the dimension of the terminal selecting device area than that of the actual functioning macro area. Thus, the dimension of a single macro area as a whole becomes expanded.
Because of this, when a plurality of macro blocks 1010 of Patent Document 4 are used, for example, areas SA occupied by the terminal selecting devices become increased as shown in FIG. 35. Thus, the actual functioning macro area cannot be utilized effectively. Further, it becomes necessary to provide elements used exclusively for the terminal selecting devices other than elements for the actual functioning macro areas, so that the number of the elements becomes increased. To provide such function parts used exclusive for connection other than those functioning originally as macro circuits in the macro blocks 1010 results in useless increase in the number of elements and wirings, which causes delay in the operation speed of the entire chip.
With Patent Document 5, the wiring (net) between each unit (macro block) is detoured, so that the wiring length becomes increased.